The present invention relates to a semiconductor device and its manufacturing method, and more particularly, it relates to a semiconductor device having a trench-gate structure and to a method of manufacturing it.
Semiconductor devices, such as a trench-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor), are used for various kinds of fields including electric power switching.
For example, a small trench-gate MOSFET is used in a personal computer as a switching element with high-speed clock frequency of about 500 kHz in order to drop a power supply voltage to a power supply levels of CPU and various disk drives (for example, 1.7 volts).
With regard to these semiconductor devices, it is desired to increase the efficiency for energy saving. In order to satisfy the requirement, it is effective to reduce conduction loss of the element, i.e., to reduce “ON resistance (Ron).”
Therefore, it has been tried to reduce the ON resistance by miniaturizing the cells. Particularly, it becomes possible to extend a channel width and increase a density sharply, by using the “trench gate structure” as the element structure.
FIG. 11 is a schematic diagram showing the sectional structure of a semiconductor device which was attempted by the Inventor of the present invention in the course of attaining this invention. That is, this figure expresses a cross-sectional structure near the gate of an n channel type MOSFET of trench gate type. An n-type epitaxial region 6 and a p-type base region 5 are laminated in this order on an n+ type substrate 7. And the trenches which intrude into the epitaxial layer 6 are formed from the surface. In the trench, an embedded gate which consists of a gate insulating film (gate oxide) 3 and an embedded gate electrode 1 is provided.
Interlayer insulation films 4 are appropriately provided on the embedded gates, and n-type source regions 2A and p+ type source regions 2B are provided around the top of the trenches, respectively. And a drain electrode 8 is appropriately provided in the back side of the substrate 7.
In this MOSFET, by applying a predetermined bias voltage to the gate electrodes 1, channel regions are formed in the circumference of the embedded trenches, and switching operation which turns the region between the source regions 2A and the drain regions into “ON” state is carried out.
Now, in such a semiconductor device, it is required not only to reduce “ON resistance”, but also to reduce a switching loss (Qsw) in order to improve the efficiency of operation. In order to reduce the switching loss, it is important to reduce the “parasitic capacitance” of the element and thus increase the operation speed.
For example, in the case of performing inverter control by combining a plurality of switching elements, when a operation speed of an element is slow, it becomes necessary to set the “dead time” which makes all the switching elements that constitute an arm in an “OFF” state longer in order to prevent the penetrating current. Therefore, the switching loss arises.
In contrast to this, if the parasitic capacitance of the switching element is reduced and thus the operation speed becomes high, the “dead time” can be shortened and the loss can be reduced.
The parasitic capacitance of the semiconductor device illustrated in FIG. 11 can be divided into some components.
First, the capacity (Cgd) between the drain and the gate can be mentioned. The capacity (Cgd) is produced in the portion where the epitaxial region 6 and the gate oxides 3 are in contact.
Next, the capacity (Cds) between the drain and the source can be mentioned. This capacity is produced in the p-n junction part where the epitaxial region 6 and the base region 5 are in contact.
Moreover, the capacity (Cgs) between gate and source can be mentioned. This capacity is produced in the portion where the gate oxide 3 and the source regions 2A, and the gate oxide 3 and the base region 5 are in contact.
Since all of these capacitance components give rise to a loss to switching operation of the semiconductor device, it is necessary to reduce these capacities. And it is effective for reducing the capacitance to reduce the capacity (Cgd) between the drain and the gate especially among these capacitance components.
Possible methods to reduce these parasitic capacitances include making the area of the contact part smaller, and accelerating the depletion by lowering the carrier concentration of each semiconductor region. However, when using these methods, there is a problem that “ON resistance” and “parasitic capacitance” or “breakdown voltage” of the semiconductor device are in a relation of a trade-off. Therefore, the improvement of the whole performance was difficult.
Structures where Cgd may be reduced by thickening the thickness of the gate oxide at the bottom of the trench are disclosed in Japanese Patent Laid-Open Publication No. 2002-299619 and Japanese Patent No. 2917922
However, according to the Inventor's original investigation, it has tuned out that in the case of the structures disclosed in these documents, there was a problem that the reduction of the ON resistance (Ron) and the reduction of the switching loss (Qsw) are not compatible.